1. Field of the Invention
The present invention relates to a programmable logic array, and is more particularly concerned with a programmable logic array constructed in ECL technology having a product matrix wherein all input lines for true and inverted matrix control signals, connected to the outputs of input amplifiers, are linked to all product term lines by non-inverting coupling elements connected over disconnectible connections and all product term lines are connected to the inputs of product term converters, and having a sum matrix wherein the outputs of the product term inverters are connected to the input lines of the sum matrix and the input lines are linked to all sum term lines by non-inverting coupling elements connected over disconnectible connections, and all sum term lines are connected to the inputs of inverting output amplifiers whose outputs form the outputs of the logic array.
2. Description of the Prior Art
Programmable logic arrays (PLA) are known in a multitude of integrated embodiments in terms of their general logical design and the selection of the logic elements (cf. "Electronic Design", 29 (1981), No. 4, pp. 12-124). Each programmable logic array contains two matrices. By way of non-inverting and inverting amplifiers, the input variables control the potentials of the input lines of the AND or, respectively, product matrix present in pairs. In the final condition of the logic array, coupling elements with whose assistance logic operations of non-inverted and/or inverted input signals are executed are effective at intersections of the input lines with product term lines selected in accordance with the programming of the logic array.
The product term lines form, if necessary given interposition of inverters, the input lines of the OR or, respectively, sum matrix. Here, also, coupling elements which need not necessarily be identical to the coupling elements in the product matrix are effective at intersections of the input line with the sum term lines selected in accordance with a programming rule. Non-inverting or inverting amplifiers are generally connected to the sum term lines, the logic results of the programmable logic array being available at the outputs of such amplifiers.
In the manufacture of programmable logic arrays, coupling elements are generally disposed at all occurring intersections in both matrices and are connected to the intersecting matrix lines over disconnectible connections (fusible links). Only when a specific use is determined, i.e. the desired logic operation functions concerning all outputs are known, is a portion of the coupling elements suppressed by the "programming" at the manufacturer or the user by destroying the disconnectible terminal connections. Likewise, errors which already existed in the unprogrammed array can only now be perceived by checking the logical functions.
Although the use of programmable logic arrays excellently offers the possibility, within limits, of realizing arbitrary logic operations without special matching of the integration masks to the respective requirements, one should not overlook that the programming operation still represents a relatively involved step proceeding to the final fabrication of the logic array. Therefore, it would be desirable to check a programmable logic array before programming. This is opposed, however, by the following provisions:
(a) as internal lines, the outputs of the product matrix are not contactible. The same also frequently applies to outputs of the sum matrix when, in particular, further circuit arrangements follow the programmable logic array within an integrated module; PA1 (b) both the non-inverting and the inverting outputs of all input amplifiers coupled to all product term lines so that changes of the binary values of the input variables do not penetrate to the potentials of the product term lines; and PA1 (c) all product term lines are connected to all sum term lines so that individual faulty or not-completely connected coupling elements are not noticeable. PA1 (a) the cathodes of diodes are connected to all product term lines, their anodes being connected to a shared product matrix test terminal; PA1 (b) the sum matrix is divided into the smallest possible number of sum sub-matrices with separate sum term lines, whereby each sum sub-matrix may exhibit, at most, as many input lines as there are input amplifiers; PA1 (c) the mutually corresponding sum term lines of a plurality of sum sub-matrices are logically linked by additional logic elements according to the operational functions valid within the sum sub-matrices; PA1 (d) the cathodes of diodes are connected to all sum term lines, their anodes being connected to a shared sum matrix test terminal; and PA1 (e) diodes are disposed in the forward conducting direction between the inverting outputs of the input amplifiers and the input lines of the sum matrix or, respectively, of the sum sub-matrices such that all input lines of the sum matrix are covered, given a plurality of sum sub-matrices, by a cyclically repeated involvement of the inverting outputs of the input amplifiers and each input lines is connected over a diode to only one output of an input amplifier. PA1 (a) a center level is applied to all inputs of the logic arrangement, the center level lying between the high signal level and the low signal level of the input variable; PA1 (b) the high signal level is individually successively applied to the respective inputs while retaining the center level at the remaining inputs; and PA1 (c) the low signal level is successively individually applied to the respective inputs upon retention of the center level at the remaining inputs. PA1 (a) the high signal level is applied to all inputs of the logic array; and PA1 (b) a level, superelevated in comparison to the high signal level by at least three diode threshold voltages, is individually successively applied to the respective inputs upon retention of the high signal level to the remaining inputs.